We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 21452

Xilinx HSPICE models may conflict with third-party HSPICE models


General Description

When using Xilinx HSPICE models in conjunction with third-party HSPICE models, an error may result if the two libraries contain models or parameters with the same name.

This may happen with Virtex-II and Virtex-II Pro HSPICE libraries. The Virtex-4 HSPICE library was created with unique Xilinx nomenclature for all models and parameters, so there should be no conflicts.

In the case of like-named models (.model), simulation will stop with an error message similar to the following:

"<card> attempted to re-define <model>"

In the case of like-named parameters (.param), the simulation will complete. However, the results may be inaccurate since the simulator will overwrite the first parameter definition encountered with the last parameter definition encountered.


You can work around this problem by manipulating the scope of the library contents. Since libraries defined with the ".lib" statement are always global in scope (and thus subject to conflict with other libraries), the contents of one of the conflicting libraries will have to be inserted into subcircuits that employ that library.

It is sufficient to insert library contents only into subcircuits appearing at the top level of the SPICE deck, as those contents will be available to any subcircuits defined within the top level subcircuit. For example, the Virtex-II Pro HSPICE release employs a single 'xlnx_rec' receiver subcircuit whose behavior (e.g., LVCMOS, LVDS, etc.) is defined by bit settings passed into the subcircuit. In this case, Xilinx library contents need only be copied once into the 'xlnx_rec' subcircuit, as this will give any underlying subcircuits visibility into the library contents.

The above procedure will work with encrypted library contents.

Note that Xilinx libraries have SS, TT, and FF corners. The procedure outlined above must be performed separately for each corner that you would like to simulate.

AR# 21452
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article