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AR# 2146

8.1i CPLD XC9500/XL/XV CPLDFit - How do I place a macrocell/signal in low-power mode?

Description

Keywords: 7.1i, 6.3i, 6.2i, 6.1i, 5.2i, 5.1i, 4.1i, 3.1i, 2.1i, 1.5i, XC9500, 9500, 9500XL, 9500XV, macrocell, low power, lowpwr, pwr_mode

In Foundation ISE/WebPACK, you can use a global option in the Fitter properties to set the default power mode for all macrocells. The options are Standard, Low, or Timing-Driven:

- "Standard" specifies that all macrocells are in high-speed mode.
- "Low" specifies that all macrocells are in low-power mode.
- "Timing-Driven" specifies that macrocells are in low power mode if they can remain so while meeting the given timing constraints.

In Design Manager (M1.x/2.1i/3.xi), this same option exists under Design -> Implement -> Edit Template.

However, depending on your design-entry approach, there are several ways to place a particular macrocell/signal in low-power mode in the design itself by using the LOWPWR (for XACT-CPLD) or PWR_MODE (for M1.x and later) attributes.

The following are described below:
Solution 1: Schematic and UCF
Solution 2: ABEL
Solution 3: XST VHDL
Solution 4: XST Verilog

For more information on PWR_MODE, please consult the Libraries Guide.

Solution

1

To apply the low power mode via the UCF, use:
net mynet PWR_MODE = LOW;
or
inst myinstance PWR_MODE = LOW;

If you change the global default to Low power, and want to specify high speed for particular macrocells, replace "LOW" with "STD".

Schematic
1. Double-click the instance on which you want to place the attribute.
2. Click "New".
3. Enter "pwr_mode" in the Attribute Name field.
4. Enter "low" for low power, or "std" for high speed.
5. Click "OK".

2

ABEL

ABEL includes the following property statement:

xilinx property 'pwr_mode low signal_1 signal_2';

This statement places signal_1 and signal_2 in low power mode. The remaining signals in the design remain in default power mode, which is "Standard" if the global option is not changed.

Example
The following XABEL example shows how to use the XEPLD property PWR_MODE statement:

module PWRTEST
Title 'pwrtest'

" D F/F with asynchronous Reset

Declarations:

DIN PIN;
CLK PIN;
RESET PIN;
DOUT PIN istype 'reg';

xilinx property 'pwr_mode low dout';

Equations:

DOUT.CLK = CLK;
DOUT.ACLR = RESET;
DOUT := DIN;

end PWRTEST

3

XST VHDL

Make the following declaration once:
attribute PWR_MODE : string;

Then, make the following declaration once for every signal that you want to place in Low power mode:
attribute PWR_MODE of signal_name : signal is "low";

Example Code

library IEEE;
use IEEE.std_logic_1164.all;

entity simple is
port (
din : in std_logic;
clk : in std_logic;
reg_out : buffer std_logic );
end simple;

architecture simple_arch of simple is
attribute PWR_MODE : string;
attribute PWR_MODE of reg_out : signal is "low";
begin

process (din, clk)
begin
if (clk'event and clk= '1') then
reg_out <= din;
end if;
end process;

end simple_arch;

4

XST Verilog

Make the following declaration for each equation that you want to place in Low power mode (the comment delimiters are intentional):
//synthesis attribute PWR_MODE of reg_out is "low";

Example Code

module ver_simple(din,clk,reg_out);
input din;
input clk;
output reg_out;

reg reg_out;

//synthesis attribute PWR_MODE of reg_out is "low";

always @(posedge clk)
begin
reg_out <= din;
end
endmodule
AR# 2146
Date Created 04/30/1997
Last Updated 11/12/2006
Status Active
Type General Article