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AR# 21484

Formality/Conformal/eCheck, Virtex-4 - How do I get the formal tools to successfully verify a design with the DCM Autocalibration Logic in it?

Description

How do I get the formal tools to successfully verify a design with the DCM clock stopped macro in it?

Solution

To work around the problem for Synopsys Formality:

A TCL script provided by Synopsys aids in successful formal verification of the design. The files can be found at:

http://www.xilinx.com/txpatches/pub/utilities/3rdparty/formality_dcm_autocalib_workaround.tar.gz

These files can be extracted to any directory:

>gunzip formality_dcm_autocalib_workaround.tar.gz

>tar -xvf formality_dcm_autocalib_workaround.tar.

Once the TCL script is extracted, it can be executed from the Formality Script file by including the following in the script file:

source setConstant.tcl

Below is an example script file:

read_verilog -r auto_calib_ecn_postngd.v -vcs "-y $env(Xilinx)/verilog/formality/simprims +libext+.v"

set_top -auto

read_verilog -i auto_calib_ecn_postpar.v -vcs "-y $env(Xilinx)/verilog/formality/simprims +libext+.v"

set_top -auto

source setConstant.tcl

verify

For more information on how to run the verification with Formality, contact Synopsys at:

Tel: 1-800-245-8005

E-mail: support_center@synopsys.com

Support Web Site: www.synopsys.com

FTP Site: ftp.synopsys.com

To work around the problem for Cadence Conformal:

There is a TCL script provided by Cadence that aids in successful formal verification of the design. The files can be found at:

http://www.xilinx.com/txpatches/pub/utilities/3rdparty/conformal_dcm_autocalib_workaround.tar.gz

These files can be extracted to any directory:

>gunzip conformal_auto_calib_workaround.tar.gz

>tar -xvf conformal_auto_calib_workaround.tar

Once the TCL script is extracted, it can be executed from the Conformal Script file by including the following in the script file:

source cfm_set_constraints.tcl

Below is an example script file:

set log file lec.log -replace

set undriven signal 0 -both

read design -f verilog.vc auto_calib_ecn_postngd.v -gol

read design -f verilog.vc auto_calib_ecn_postpar.v DCM_STANDBY_ecn.v -rev

Note1: The DCM_STANDBY_ecn.v is just an example that is used for illustration purposes. This is the output file from netgen.

Note2 : Verilog.vc file points to the location of the Downloaded libraries.

Example of contents of Verilog.vc

-y $XILINX/verilog/verplex/unisims

-y $XILINX/verilog/verplex/simprims

tclmode

source ../tcl/cfm_set_constraints.tcl

set_constraints

vpxmode

set sys mode lec

add compare point -all

compare

usage

For more information on how to run the verification with Conformal, contact Cadence at:

Phone: 1-877-237-4911

Email: support@cadence.com

Support Web Site: sourcelink.cadence.com

General Web Site: www.cadence.com

FTP Site: ftp.cadence.com

To work around the problem for Prover eCheck:

When using eCheck, the design will have to fail first on the DCM clock stopped Macro.

If a gate-to-gate comparison fails for an instance of the black box X_DCM_ADV, open the counter example for the input pin RST to this black box.

Identify the name of the implementation design register in the fan-in of the counter example. This name can, for instance, be:

physical_group_locked_OBUF/dcminst1/q/f1/q

In your Prover eCheck TCL script, add the following constraint to tie the above register to zero:

constraint -add -reg -custom physical_group_clk_dcmo/dcminst1/q/f1/q 0 impl

Re-run the comparison and repeat if there are more instances of failing X_DCM_ADV black boxes.

For more information on how to run the verification with eCheck, please contact Prover Technologies at:

Tel: +1-650-722-2750

Fax: +1-650-347-6284

Email: echeck-support@prover.com

AR# 21484
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article