When generic C_SUPPORT_BURST is False, and PLB IPIF is used in pure master configuration (not master-slave), certain signals are not initialized (not in Bus_Reset, as in default configuration), but are used within "if statements" in read mode. This causes master accesses to not generate M_Request on the bus.
Signals have value 'U', even after reset is over.
Look at :
The PLB IPIF that is incorporated by the Wizard for the User Master support must always have bursting enabled. This is a known issue for the User Master enabled.
Make sure that your design has overridden the defaults (False) of these two PLB IPIF parameters by setting them to True in the PLB IPIF instance:
C_DEV_BURST_ENABLE : BOOLEAN := true;
Burst Enable for IPIF Interface (and cacheline support)
C_DEV_FAST_DATA_XFER : Boolean := true;
If Burst is enabled, then this parameter allows the selection of a fast data transfer mode of one clock per data beat (FPGA-resource intensive) or a slower multi-clock per data beat transfer mode (saves FPGA resources).
This problem will be fixed in the next release of EDK.