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AR# 21529

ISIM Simulator - "ERROR:HDLParsers:3281 - "C:/xxx/<file_name>.vhd" Line 74. behavioral is not an architecture body for blkmemdp_v6_2 in library XilinxCoreLib."


Keywords: CORE Generator, CORE Generator, distributed, block memory, out, space, virtual, swap, FIFO, simulator, simulation, behavioral, Verilog, VHDL, ISE, ip, update, cores, logicores

When I try to simulate the cores released in 7.1i IP Updates using ISIM Simulator, the following error occurs:

"ERROR:HDLParsers:3281 - "C:/case_attach/581474/coregen/vhdl/ram_core.vhd"
Line 74. behavioral is not an architecture body for blkmemdp_v6_2 in library XilinxCoreLib.
Parsing "fifo_2048x8_tb_stx.prj": 0.95"


This error is issued by ISIM Simulator which calls HDL Parser for syntax check. It cannot find the pre-compiled library for the Blkmemdp_v6_2. This will happen for all the IPs released in 7.1i IP Updates, as the pre-compiled libraries for IP Updates do not exist.

The support for ISIM Simulator in regards to IP cores will be available shortly. Meanwhile, there are a couple of options you can try:

1. Generate structural model rather than behavioral model for simulation. You can select this in the CORE Generator project option. The structural-based models are UniSim-based models. Therefore, you should be able to simulate using ISIM.

2. Performing gate-level (post-translate or post-PAR) simulation.

AR# 21529
Date Created 09/04/2007
Last Updated 08/24/2009
Status Archive
Type General Article