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AR# 21568

7.1i Virtex-4 PAR - Incomplete message about turning off Regional Clock placement

Description

Keywords: MAP, -timing, placer

When I run MAP with the -timing option, my design fails with the following messages regarding placement failures:

"ERROR:Place:543 - Due to placement constraints, the following 1 components
cannot be placed. The relative offsets of the components are shown in
brackets next to the component names.
FF imac/mr_top/mac_readblock/mac_rdwt2/BBD_dat_1[1] (0, 0)"

(Previous message repeated for other components)

ERROR:Place:545 - The placement constraints may have been generated by the
Regional Clock placer. To allow map -timing to complete, please try running
map -timing with Regional Clock placement turned OFF.

There is also a message stating that the placement failures might be due to something called "Regional Clock placer" and that I should disable it. What does this mean?

Solution

The "Regional Clock Placer" is a placement algorithm that attempts to place the loads of a regional clock (clock net driven by a regional buffer, BUFR, rather than a global buffer, BUFG) in such a way that they can be routed in the clock regions available to the buffer. This algorithm creates some internal area constraints that, when combined with user constraints, can make the design difficult to place successfully and results in the errors mentioned.

The Local Clock Placer can be disabled by setting the following environment variable:

Windows:
SET XIL_PAR_NOIORGLLOCCLKSPL=1

Linux and Solaris:
setenv XIL_PAR_NOIORGLLOCCLKSPL 1

NOTE: Prior to 7.1i SP3, the variable name was PAR_NOIORGLLOCCLKSPL. Both will work in SP3 and later versions.

For general information about setting ISE environment variables, see (Xilinx Answer 11630).

AR# 21568
Date Created 09/04/2007
Last Updated 10/20/2008
Status Archive
Type General Article