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AR# 21569

7.1 EDK - Processor IP Core, the XST tool in 7.1 EDK and higher is using one additional BUFG than 6.3 EDK for OPB SPI and other cores

Description

General Description:

The XST tool in 7.1 EDK and higher is using one additional BUFG than the 6.3 release did. This is causing my design to not fit with the new software release.

Solution

To work around this issue, follow these instructions:

To eliminate this additional BUFG, add the following lines/attribute to the "spi_module.vhd" located in the "<edk>\hw\XilinxProcessorIPLib\pcores\opb_spi_v1_00_c\hdl\vhdl" directory.

attribute buffer_type : string;

attribute buffer_type of SCK_SR_local : signal is "none";

After adding these attributes, clean and re-generate your project design.

The above solution will work with other Processor IPs, if you apply the attribute to the correct signals in the HDL code

AR# 21569
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article