AR #21576 - Virtex-4 RocketIO - 7.1i PAR does not allow a connection between the GT11 clock inputs and BUFR

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Virtex-4 RocketIO - 7.1i PAR does not allow a connection between the GT11 clock inputs and BUFR

AR#	21576
Part	FPGA-RocketIO
Last Modified	2005-07-11 00:00:00.0
Status	Active
Keywords	PAR, 7.1i, GT11, BUFR

Description

Keywords: PAR, 7.1i, GT11, BUFR

Urgency: Standard

General Description:
7.1i PAR does not allow the GT11 input clocks to be driven by BUFRs. These include USRCLKs.

Solution

This issue is under investigation, and whether this use model will be supported in the design tools will be resolved by ISE 8.2i.

GT11 input clocks can be driven by BUFGs.

There is no restriction on GT11 clock outputs driving either a BUFR or a BUFG.