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AR# 21585

7.1i IP Update 1 Dual Port Block Memory v6.2 - Memory initialization does not work (all locations set to zero)


Keywords: COREGen, RAM, init, mif, coe, initialize

I generated a Dual Port Block RAM using COREGen 7.1 IP Update 1, and I loaded a ".coe" file to initialize the core memory. However, in both Behavioral and Post PAR simulations (and also in hardware), the memory has not been initialized properly and remains at the default value.

What is causing this problem?


The memory initialization flow is not working when generating a Dual Port Block Memory v6.2 using COREGen 7.1 IP Update 1.

This issue has been fixed in Dual Port Block Memory v6.3, which is available in CORE Generator 7.1i IP Update 3.
AR# 21585
Date Created 06/10/2005
Last Updated 12/13/2006
Status Archive
Type General Article