7.1i NetGen, Timing Simulation Virtex-4 - The OSERDES component does not have a clock to out that matches the ODDR component

Description

Keywords: simulate, SimPrim, x_oserdes, oserdes, delay, output, timing, x_oddr

During a timing simulation, there is a clock to out delay discrepancy between output of an OSERDES when compared to an ODDR. Since the ODDR is a subset of the OSERDES, this delay should match.

Solution