When does the LOCKED signal of a Virtex-II or Virtex-II Pro DCM go Low after RST has been asserted? I checked the Virtex-II User Guide but could not find any relevant information.
When the reset pin is activated, the LOCKED signal deactivates within four source clock cycles. This information will be added to the Virtex-II User Guide and is currently included in the "Virtex-II Pro and Virtex-II Pro X FPGA User Guide" in the DCM section in the Design Considerations chapter. This guide is accessible at: