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AR# 21646

LogiCORE 3GPP TCC - The 3GPP TCC Core v1.0 indicates in the CORE Generator that it does not support Virtex-4. When will it support these architectures, or can the 3GPP TCC generated for Spartan-3 be re-targeted to one of these architectures?

Description


General Description: 
The 3GPP TCC Core v1.0 indicates in the CORE Generator that it does not support Virtex-4. When will it support these architectures, or can the 3GPP TCC generated for Spartan-3 be re-targeted to one of these architectures?

Solution


The FPGA fabric for the Virtex-II/-II Pro/-4 and Spartan-3 are similar. The fundamental difference between the Virtex-4/Spartan-3 and the Virtex-II/-II Pro is the CLB with two normal slices (SliceM) and two non-SRL16E/RAM16x1 (SliceL). As long as Relationally Placed Macros (RPMs) are not used, these differences do not affect using the Spartan-3 Core in a Virtex-4.  
 
To use the core for Virtex-4, follow these steps: 
1. Change the device for your ISE project to Spartan-3. 
2. Select "Add a New Source" (to your ISE project) and select COREGen IP. 
3. Run the COREGen GUI and generate the 3GPP2 TCC Core. 
4. Change the device for your ISE project back to Virtex-4. 
5. Instantiate the Core in your top-level source. 
6. If the Core needs to be re-parameterized, repeat steps 1-4. 
7. Before implementing your design, ensure that RPMs are turned off. 
 
NOTE: The performance numbers for the area and speed will be different for Virtex-4 than for Spartan-3 implementations of the 3GPP2 TCC.
AR# 21646
Date Created 09/04/2007
Last Updated 05/19/2014
Status Archive
Type General Article