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AR# 21647

LogiCORE Reed Solomon Encoder v5.0 - Why do the check symbols appear to be wrong with I do a Verilog Structure of Behaviors simulation?

Description

Keywords: IP, CORE Generator, Reed Solomon, Encoder, v5.0, Simulation Model, Structure of Behaviors

Urgency: Standard

General Description:
Why do the check symbols appear to be wrong with I do a Verilog Structure of Behaviors simulation?

Solution

1. Some people may be using this flow, if they do not want to do a mixed mode simulation, where the Verilog calls the VHDL RS Encoder Simulation model. This is the recommended flow and should be used if at all possible.

2. The second optoin would be to use a unisim model for simulation.
For more information, please see (Xilinx Answer 8065).

3. If either of these flows is not possible you will need to modify one of the system files for the Reed Solomon Encoder to work around the check symbol generation problem.

1) From the file $XILINX/coregen/ip/xilinx/dsp/com/xilinx/ip/rs_encoder_v5_0/rs_encoder_v5_0.xcd
Remove line 21 => "override_simulationfiles = behavioral"
($XILINX is the path to the Xilinx install on your machine)

2) Restart Core Generator.

3) Change the Core Generator project options to generate the verilog model from the netlist.
From the Xilinx Core Generator Window select the Menu Item
Project> Project_Options
From the Project Options Window select the tab
"Menu Generation"
Under "Flow" select "Select Custom Output Products"
Under "Simulation Files" select "Structrual" and "Verilog"

4) Save the project.

5) Regenerate (Under current Setting) the RS_Encoder_v5_0.


Please See (Xilinx Answer 30177) for a detailed list of LogiCORE Reed Solomon Encoder Release Notes and Known Issues.
AR# 21647
Date Created 06/23/2005
Last Updated 05/13/2009
Status Archive
Type General Article