The fitter report equations in VHDL for the FDCPE and FTCPE are missing a port connection. The legend shows that these components have six ports; however, the equations show five. How do I identify which signals connect to which ports?
The port connection that is missing is the Clock Enable (CE) connection. If a CE is used, six ports are shown. If a CE is not used, only five are shown and you can assume that the CE is '1'.
This issue will be fixed in a future release of the design tools.