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AR# 21658

LogiCORE PCI-X - How to use the DCM_STANDBY macro with the PCI-X Core? Is the PCI-X core affected by silicon stepping and the new DCM timing parameters on Virtex-4 devices?

Description

General Description:

Is the PCI-X Core affected by silicon stepping and the new DCM timing parameters on Virtex-4 devices? Does the PCI-X Core need to use the DCM_STANDBY marco?

Solution

Designers using the PCI-X Core on Virtex-4 devices should review (Xilinx Answer 21605) for information on Virtex-4 silicon stepping levels.

The PCI-X Core does make use of a DCM, so users must also review (Xilinx Answer 21127). This is a general Answer Record describing how the new DCM parameters added to the Virtex-4 Data Sheet affects the operation of the device.

After reviewing these solutions, users might find that they need to manually insert the DCM_STANDBY module to the PCI-X Core in place of the normal DCM, depending on the stepping level of their targeted device. The DCM in the PCI-X Core is instantiated in the wrapper file so users can add this module. The wrapper file used for PCI-X designs in a Virtex-4 is titled pcix_lc_64x.v or pcix_lc_64x.vhd.

VHDL

In the file pcix_lc_64x.vhd found under <install path>/vhdl/src/wrap directory, you will find the following component declaration:

component CLKDLL

port (

CLKIN : in std_logic;

CLKFB : in std_logic;

RST : in std_logic;

CLK0 : out std_logic;

CLK90 : out std_logic;

CLK180 : out std_logic;

CLK270 : out std_logic;

CLK2X : out std_logic;

CLKDV : out std_logic;

LOCKED : out std_logic

);

end component;

Replace this with the component declaration of the DCM_STANDBY macro:

component dcm_standby

PORT (

CLK0 : OUT std_logic;

CLK180 : OUT std_logic;

CLK270 : OUT std_logic;

CLK2X : OUT std_logic;

CLK2X180 : OUT std_logic;

CLK90 : OUT std_logic;

CLKDV : OUT std_logic;

CLKFX : OUT std_logic;

CLKFX180 : OUT std_logic;

DO : OUT std_logic_vector(15 DOWNTO 0);

LOCKED : OUT std_logic;

PSDONE : OUT std_logic;

CLKFB : IN std_logic;

CLKIN : IN std_logic;

PSCLK : IN std_logic;

PSEN : IN std_logic;

PSINCDEC : IN std_logic;

RST : IN std_logic);

end component;

Next you will find the CLKDLL and BUFG instantiation:

XPCI_DLL : CLKDLL port map

( CLKIN => CLK_NUB, CLKFB => DFC, RST => BUS_RST, CLK0 => CLK_OUT,

CLK90 => NC90, CLK180 => NC180, CLK270 => NC270,

CLK2X => NC2X, CLKDV => NCDV,

LOCKED => NCLCK);

XPCI_CLK2 : BUFG port map

( O => CLK, I => CLK_OUT );

Replace this with the DCM_STANDBY instantiation and comment out the BUFG instantiation.

XPCI_DLL : dcm_standby port map

( CLKIN => CLK_NUB, CLKFB => CLK, RST => BUS_RST, CLK0 => CLK,

CLK90 => NC90, CLK180 => NC180, CLK270 => NC270,

CLK2X => NC2X, CLKDV => NCDV,

LOCKED => NCLCK,

CLK2X180 => NCCLK2X180, CLKFX => NCCLKFX, CLKFX180 => NCCLKFX180,

DO => NCDO, PSDONE => PSDONE, PSCLK => LO, PSEN => LO, PSINCDEC => LO);

-- XPCI_CLK2 : BUFG port map

-- ( O => CLK, I => CLK_OUT );

Note that the DCM_STANDBY module inserts a BUFG on the CLK0 output of the module. Due to this, the BUFG in the wrapper file must be removed or commented out as shown above. Further notice that the CLK0 output is connected to CLK now and not CLK_OUT since the BUFG instantiation in the wrapper was removed.

The DCM_STANDBY module found in the dcm_standby.vhd file referenced in (Xilinx Answer 21127) can then be copied into the wrapper file and placed at the end of the file. Also, the entities found in the ringregosc.vhd and counter.vhd file can be copied into the bottom of the wrapper file. Alternatively, users can add these files to the synthesis project.

Verilog

In the file pcix_lc_64x.v found under <install path>/verilog/src/wrap directory, you will find the following instantiation:

CLKDLL XPCI_DLL (.CLKIN(CLK_NUB), .CLKFB(CLK), .RST(BUS_RST), .CLK0(CLK_OUT),

.CLK90(NC90), .CLK180(NC180), .CLK270(NC270),

.CLK2X(NC2X), .CLKDV(NCDV),

.LOCKED(NCLCK));

The CLKDLL reference should be replaced by dcm_standby as follows:

dcm_standby XPCI_DLL (.CLKIN(CLK_NUB), .CLKFB(CLK), .RST(BUS_RST), .CLK0(CLK),

.CLK90(NC90), .CLK180(NC180), .CLK270(NC270),

.CLK2X(NC2X), .CLKDV(NCDV),

.LOCKED(NCLCK));

// BUFG XPCI_CLK2 (.O(CLK),.I(CLK_OUT));

Note that the DCM_STANDBY module inserts a BUFG on the CLK0 output of the module. Due to this, the BUFG in the wrapper file must be removed or commented out as shown above. Further, notice that the CLK0 output is connected to CLK now and not CLK_OUT since the BUFG instantiation in the wrapper was removed.

The DCM_STANDBY module found in the dcm_standby.v file referenced in (Xilinx Answer 21127) can then be copied into the wrapper file and placed at the end of the file--Verilog allows for multiple modules per file. Alternatively users can follow suggestions found in (Xilinx Answer 21127) to make this module available in their projects.

UCF File Changes

The UCF file must be changed so that the constraints can be applied to the DCM instanitated inside the DCM_STANDBY module. Current UCF file constraints are as follows:

INST "XPCI_WRAP/XPCI_DLL" CLKOUT_PHASE_SHIFT = FIXED ;

INST "XPCI_WRAP/XPCI_DLL" DESKEW_ADJUST = 22 ;

INST "XPCI_WRAP/XPCI_DLL" PHASE_SHIFT = +0 ;

INST "XPCI_WRAP/XPCI_DLL" LOC = "DCM_ADV_X0Y2" ;

These must be modified as follows:

INST "XPCI_WRAP/XPCI_DLL/dcminst1" CLKOUT_PHASE_SHIFT = FIXED ;

INST "XPCI_WRAP/XPCI_DLL/dcminst1" DESKEW_ADJUST = 22 ;

INST "XPCI_WRAP/XPCI_DLL/dcminst1" PHASE_SHIFT = +0 ;

INST "XPCI_WRAP/XPCI_DLL/dcminst1" LOC = "DCM_ADV_X0Y2";

Implementation

As noted in (Xilinx Answer 21127), users must set the environment variable XIL_MAP_ALLOW_ANY_DLL_INPUT to YES; otherwise, MAP will fail.

AR# 21658
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article