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AR# 21660

7.1i ISE - CPLD Design Flow, Generate Post Fit Sim - An error occurred while executing "C:/Xilinx_7.1/data/projnav/scripts/TclFileWrapper4Halite.tcl"


Keywords: Post Fit; Sim Model; cpld; CoolRunner-II; Tcl; Wrapper4Halite; error, xapp800

Urgency: Standard

General Description:
When running a CoolRunner-II design through the Implementation process, I receive the following error when the tools try to Generate Post-Fit Simulation Model:

"An error occurred while executing C:/Xilinx_7.1/data/projnav/scripts/TclFileWrapper4Halite.tcl"

Why am I getting this?


This is a problem that has been seen (specifically with the xapp800 design files) in the ISE 7.1i version of the tools. The problem has been fixed in ISE 8.1i version. For a temporary work-around, follow the process below:

1. Run the following command from a DOS prompt:
netgen -rpw 100 -ar Structure -xon true -w -ofmt vhdl -sim <top_level>.nga <top_level>_timesim.vhd
where <top_level> should be replaced by the file name of the top level HDL / Schematic source

2. Compile the "glbl.v" module, the generated simulation model, and the testbench. For example:
vlog $env(XILINX)/verilog/src/glbl.v <design_name>_timesim.v <testbench>.v

For more information about the "glbl.v" module, see (Xilinx Answer 6537).

3. Load the design in ModelSim and use the -L switch to point to the Verilog SimPrim models that define the behavior of the components in the simulation model. The "glbl" needs to be loaded as well.
vsim -t ps -L simprims_ver work.<testbench> work.glbl

The SDF file with the timing information is automatically loaded. See (Xilinx Answer 10651) for more information.

NOTE: The "glbl.v" automatically pulses Global Set/Reset (GSR) for the first 100 ns of the simulation. See (Xilinx Answer 6537) for more information.

AR# 21660
Date Created 06/24/2005
Last Updated 12/13/2006
Status Archive
Type General Article