We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 21667

9.1i FPGA Editor - Editblock operation results in DRC errors


When I edit a component in the FPGA Editor, the resulting configuration causes many DRC errors similar to the following:

"#ERROR:PhysDesignRules:792 - Illegal configuration for block comp_name The cell <GT_GT> has the following precondition programming <IOSTANDARD>:<CUSTOM>. The cell <GT_GT>, must have the following programming <CHAN_BOND_SEQ_1_1> with a length of <11>. The cell <GT_GT>, must have the following programming <CHAN_BOND_SEQ_1_1>:<[0-1]+>."

"ERROR:PhysDesignRules:815 - The pin <BREFCLK2> of block <i_rsl_a2/aurora_module/lane_0_mgt_i> is used but has no parent signal. "

Two problems occur in this situation:

- Some of the original parameter settings are lost, causing the first error.

- The "child signals" internal to the component are incorrectly created, causing the second error.


The DRC errors are introduced when the component is edited. When all editing is complete, you must select the edited component and then run the "trim" command in the command window at the bottom of the editor to remove the child signals for that component.

NOTE: This solution can potentially cause problems as follows:

- The internal connectivity is removed for components that have incomplete external connectivity. Do not run "trim" on components with incomplete external connectivity.

- There are some valid component configurations in which external connectivity is left incomplete for some pins with the expectation that BitGen will tie these pins Low. For example, this can be the case with RAM address pins. These types of components cannot currently be edited using the FPGA Editor because it is not possible to run "trim" afterwards without corrupting the component configuration.

AR# 21667
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article