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AR# 21696

LogiCORE SPI-4.2 (POS-PHY L4) Lite - How are the SPI-4.2 Lite cores affected by new Virtex-4 DCM parameter requirements?

Description

General Description: 

How are the SPI-4.2 Lite cores affected by the new Virtex-4 DCM parameter requirements? 

 

The new Virtex-4 DCM parameters and requirements are explained in (Xilinx Answer 21127)

 

If you are using the SPI-4.2 (v7.x) Core, see (Xilinx Answer 21685)

 

If you are using the SPI-4.2 Lite (v2.1) Core, see information below.

Solution

The current version of the SPI-4.2 Lite Core (v2.1) using the master clocking option and the default clocking option contains DCMs embedded within the core, and they are subject to the new DCM requirements.  

 

The following netlists, located in "/implement_*/netlists/virtex4" directory, are affected: 

pl4_lite_snk_top.edf (sink core with the embedded clocking, uses DCM) 

pl4_lite_src_top_master_addr.edf (source core with the embedded clocking, uses DCM) 

pl4_lite_src_top_master_trans.edf (source core with the embedded clocking, uses DCM) 

 

The following netlists, located in "/implement_*/netlists/virtex4" directory, are NOT affected: 

pl4_lite_snk_top_user_clk.edf (sink core without embedded clocking, does not use DCM) 

pl4_lite_src_top_slave_addr.edf (source core without embedded clocking, does not use DCM) 

pl4_lite_src_top_slave_trans.edf (source core without embedded clocking, does not use DCM) 

 

To address the requirement: 

TCONFIG: Maximum time to configure devices after VCCINT is applied (10 min), 

use the Null Bitstream solution as indicated in (Xilinx Answer 21127)

 

To address the other two requirements: 

DCM_INPUT_CLOCK_STOP: Maximum duration that CLKIN and CLKFB can be stopped (100 ms), and 

DCM_RESET: Maximum duration that RST can be held asserted (10 sec), 

follow these steps: 

 

1. Use the cores without the embedded clocking scheme provided with the core: 

For the Sink Core: use pl4_lite_snk_top_user_clk.edf 

For the Source Core: use pl4_lite_src_top_slave_addr.edf or pl4_lite_src_top_slave_trans.edf 

 

2. Since these cores do NOT contain an embedded clocking scheme, you will need to provide your own user clocking scheme or use the provided example user clocking modules: 

/spi4_2_lite_v2_1/implement_*/verilog/pl4_lite_snk_clk.v 

/spi4_2_lite_v2_1/implement_*/verilog/pl4_lite_src_clk.v  

or  

/spi4_2_lite_v2_1/implement_*/vhdl/pl4_lite_snk_clk.vhd 

/spi4_2_lite_v2_1/implement_*/vhdl/pl4_lite_src_clk.vhd 

 

3. Incorporate the DCM_STANDBY macro as indicated in (Xilinx Answer 21127).

AR# 21696
Date Created 09/04/2007
Last Updated 05/19/2014
Status Archive
Type General Article