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AR# 21700

7.1i EDK SP2 - plb_ddr 1.10a hard to meet timing in Virtex-4


General Description: 

When running designs under 7.1i EDK using plb_ddr controller V1.10.a, timing is failing on 1/4 cycle paths in DDR DQS control logic. 


In Virtex-4, to allow the set/reset signals to be shared between the OLOGIC and ILOGIC registers, since the DDR design needs to keep the DQS input registers in the IOB, we have modified the design behavior with respect to the set/reset signals in the IOB needed by the OLOGIC registers. The new logic collapses the set/reset signals into the D input of the DQS output register to improve timing.


This problem has been fixed in the latest 7.1i EDK Service Pack available at: 

The first service pack containing the fix is 7.1i EDK Service Pack 2.

AR# 21700
Date Created 09/04/2007
Last Updated 05/19/2014
Status Archive
Type General Article