We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 21701

7.1i EDK SP2 - DCR devices might errantly acknowledge requests when PPC has C_DCR_RESYNC=1 option


General Description: 

The problem occurs when you use the C_DCR_RESYNC=1 option on the ppc405. There might be errant DCR ack's. This occurs because the PPC wrapper has registers on the DCR_Read and DCR_Write signals, but not on the DCR_ABus. This was fixed by registering the DCR_Read, DCR_Write, and DCR_ABus, with a clock enable on the DCR_ABus that is asserted only when DCR_Read and DCR_Write are not asserted.


This problem has been fixed in the latest 7.1i EDK Service Pack available at: 

The first service pack containing the fix is 7.1i EDK Service Pack 2.

AR# 21701
Date Created 09/04/2007
Last Updated 05/19/2014
Status Archive
Type General Article