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AR# 21715

Virtex-4 RocketIO - CRC Design FAQ

Description

RocketIO in Virtex-4 has the flexible CRC block. This Answer Record answers the frequently asked questions for using CRC in RocketIO.

Solution

What is the polynomial built in RocketIO?

The CRC-32 Block is fixed CRC generator using the following polynomial:

G(x) = x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x + 1

What Data widths are supported for input data?

Supported data widths are 8, 16, 24, 32, 40, 48, 56 and 64 bit.

What are TX/RXCRCCLK and TX/RXCRCINTCLK?

There are two clock signals for TX and RX. TX/RXCRCCLK is the clock for the internal CRC Core. TX/RXCRCINTCLK is the fabric interface clock for TX and RX. When data width is more than 32-bit, the attribute TX/RXCRCCLKDOUBLE should be set to TRUE. But for data width less than 32-bit, TX/RXCRCCLKDOUBLE could be set to TRUE as well. When TX/RXCRCCLKDOUBLE is set to TRUE, the ratio between TX/RXCRCINTCLK and TX/RXCRCCLK frequencies is 1:2.

How do I specify the initial value for beginning of CRC calculation?

The attribute TX/RXCRCINITVAL can be set for the initial value. Default value is 32'h0.

Does CRC block check the error of packet?

No, data valid check is not done in CRC block. This must be done in the fabric to check the validity of the received packets. CRC is identical for both the transmitter and receiver operation.

How to operate CRC block?

CRC block is independent from RocketIO data flow. The fabric circuit is required to operate CRC block. The following is the example of operation.

1. Apply the appropriate clocks to CRCINTCLK and CRCCLK.

2. Initialize the CRC by asserting CRCINIT for one cycle at the beginning of each CRC calculation for every packet.

3. When the CRC calculation is required to be stopped or resumed, CRCDATAVALID should be asserted or deasserted.

4. At the end of a packet, if the remaining data width is different than that used for the rest of the packet, change the data width field to indicate the correct data input actual data width.

5. After the end of data input, wait for three interface clock cycles for the corresponding CRC field.

NOTE

The output of the CRCOUT is inverted and transmitted to the fabric to deliver the CRC value for both the transmitter and the receiver modes. To obtain the real CRC value, the CRC value should be inverted by fabric.

For detail timing, please see the Virtex-4 RocketIO MGT User Guide: Chapter 5,"Cyclic Redundancy Check(CRC)" -> Latency and Timing

Virtex-4 RocketIO MGT User Guide:

http://www.xilinx.com/xlnx/xweb/xil_publications_display.jsp?sGlobalNavPick=&sSecondaryNavPick=&category=-1210770&iLanguageID=1

AR# 21715
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article