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AR# 21716

Spartan-3E, DDR2 - The DDR_ALIGNMENT attribute does not get set properly when using schematic symbol

Description

When using either the IDDR2 or ODDR2 schematic symbol, the DDR_ALIGNMENT attribute does not get set correctly. If you set the attribute on the schematic symbol to either C0 or C1, it reverts back to "NONE."

Solution


To work around this problem, it is suggested that you instantiate the IDDR2 and ODDR2 macros in either VHDL or Verilog. A schematic symbol can be generated for your DDR2 component by highlighting the source code in the "Sources in Project" window and clicking "Generate Schematic Symbol" in the "Process For Source" widow.

You can also set the attribute in your UCF file:

INST "MY_DDR_INST_NAME" DDR_ALIGNMENT = {C1|C0|NONE};

This problem has been fixed in ISE 8.1i.

VHDL Instantiation Template

-- IDDR2: Input Double Data Rate Input Register with

-- Set, Reset and Clock Enable. Spartan-3E

-- Xilinx HDL Libraries Guide version 7.1i



IDDR2_inst : IDDR2

generic map (

DDR_ALIGNMENT => "NONE", -- Sets output alignment

-- to "NONE", "C0" or "C1"

INIT_Q0 => '0', -- Sets initial state of the Q0

-- output to '0' or '1'

INIT_Q1 => '0', -- Sets initial state of the Q1

-- output to '0' or '1'

SRTYPE =>= "SYNC") -- Specifies "SYNC" or "ASYNC"

-- set/reset

port map (

Q0 => Q0, -- 1-bit output captured with C0 clock

Q1 => Q1, -- 1-bit output captured with C1 clock

C0 => C0, -- 1-bit clock input

C1 => C1, -- 1-bit clock input

CE => CE, -- 1-bit clock enable input

D => D, -- 1-bit DDR data input

R => R, -- 1-bit reset input

S => S -- 1-bit set input

);

-- End of IDDR2_inst instantiation

Verilog Instantiation Template

// IDDR2: Input Double Data Rate Input Register with

// Set, Reset and Clock Enable. Spartan-3E

// Xilinx HDL Libraries Guide version 7.1i



IDDR2 #(

// The following parameters specify the behavior

// of the component.

.DDR_ALIGNMENT("NONE"), // Sets output alignment

// to "NONE", "C0" or "C1"

.INIT_Q0(1'b0), // Sets initial state of the Q0

// output to 1'b0 or 1'b1

.INIT_Q1(1'b0), // Sets initial state of the Q1

// output to 1'b0 or 1'b1

.SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC"

// set/reset

IDDR2_inst (

.Q0(Q0), // 1-bit output captured with C0 clock

.Q1(Q1), // 1-bit output captured with C1 clock

.C0(C0), // 1-bit clock input

.C1(C1), // 1-bit clock input

.CE(CE), // 1-bit clock enable input

.D(D), // 1-bit DDR data input

.R(R), // 1-bit reset input

.S(S) // 1-bit set input

);
AR# 21716
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article