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AR# 21755

Spartan-6 and Spartan-3 Generation FPGA DCM - How do I handle a frequency change at the input clock of my DCM?

Description


How do I handle a frequency change at the input clock of my DCM?
For example, I want to change the input frequency from 25 MHz to 26 MHz.

Solution


For the DCM to stay locked, you must follow the input clock requirements as defined in the family device data sheet. Changing the input clock frequency violates the input clock requirements and causes the DCM to unlock. Consequently, if you want to change the frequency, you must either reset the DCM or reconfigure the DCM when the new clock frequency is stable. The minimum reset pulse width specification must also be followed. This is defined in the device data sheet by the DCM_RST_PW_MIN parameter.

Spartan-3 FPGA
A reset of the DCM is warranted only when changing the input to a frequency within the supported range of the current DCM configuration (i.e., FREQUENCY_MODE = Low or High). For example, changing the input clock frequency from 25 MHz to 26 MHz requires only a DCM reset because both frequencies are in the range supported by the Low frequency mode. The reset must follow the guidelines described above.
If the new frequency is not supported by the mode setting of the current DCM configuration, you must reconfigure the DCM with the new FREQUENCY_MODE setting. For example, changing the input clock frequency from 47 MHz to 168 MHz requires a reconfiguration of the FREQUENCY_MODE attribute from Low to High. In this case, resetting the DCM is not sufficient because the two frequencies are not supported by the same frequency mode.

Spartan-3E, Spartan-3A, Spartan-3AN, and Spartan-3A DSP FPGA
The DCM for Spartan-3E/-3A/-3AN/-3A DSP FPGA does not require a frequency mode setting in software. Instead, it is detected automatically by the device and properly set. Because of this, you do not have to ever reset the frequency mode and reconfigure the FPGA if changing the input frequency. Instead, if you change the input frequency within the entire supported range, you must reset only the DCM.

Spartan-6 FPGA
The DCM for Spartan-6 FPGA does not require a frequency mode setting in software. Instead, it is detected automatically by the device and properly set. Because of this, you do not have to ever reset the frequency mode and reconfigure the FPGA if changing the input frequency. Instead, if you change the input frequency within the entire supported range, you must reset only the DCM.
If you are using the DCM_CLKGEN, there is an additional feature that may help work around unwanted input frequency drifts or changes. The Free Running Oscillator mode allows you to start the DCM by locking onto the input clock. Once LOCK goes high, the output continues toggling at the same frequency but the input is ignored until the DCM is reset again. This would ignore any changes on the input clock. Please see the Spartan-6 FPGA Clocking Resources User Guide for detailed descriptions:
http://www.xilinx.com/support/documentation/user_guides/ug382.pdf


Additional Resources
You can access the Spartan-6 FPGA data sheet at:
http://www.xilinx.com/support/documentation/data_sheets/ds162.pdf

You can access the Spartan-3A FPGA data sheet at:
http://www.xilinx.com/xlnx/xweb/xil_publications_index.jsp
Choose FPGA Device Families -> Spartan-3A -> "Spartan-3A FPGA Family Data Sheet" -- (DS529)

You can access the Spartan-3E FPGA data sheet at:
http://www.xilinx.com/xlnx/xweb/xil_publications_index.jsp
Choose FPGA Device Families -> Spartan-3E -> "Spartan-3E Complete Data Sheet (All four modules)" -- (DS312)

You can access the Spartan-3 FPGA data sheets at:
http://www.xilinx.com/xlnx/xweb/xil_publications_index.jsp
Choose FPGA Device Families -> Spartan-3/3L -> "Spartan-3 Complete Data Sheet (All four modules)" -- (DS099)

For additional information on DCM input clock requirements, refer to the Spartan-3 Generation FPGA User Guide at:
http://www.xilinx.com/xlnx/xweb/xil_publications_index.jsp?category=User+Guides
Choose FPGA Device Families -> Spartan-3/3L -> "Spartan-3 Generation FPGA User Guide" -- (UG331)

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
46790 Spartan-6 FPGA Design Assistant - Troubleshooting Common Clocking Problems N/A N/A
AR# 21755
Date Created 09/04/2007
Last Updated 02/04/2013
Status Active
Type General Article
Devices
  • Spartan-3
  • Spartan-3 XA
  • Spartan-3A
  • More
  • Spartan-3A DSP
  • Spartan-3AN
  • Spartan-3E
  • Spartan-6 LX
  • Spartan-6 LXT
  • Less
IP
  • Digital Clock Manager (DCM) Module