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AR# 21777

Virtex-4 Configuration - Excessive current draw when encryption is not implemented properly


When encryption is implemented in a Virtex-4 device, the device begins to draw excessive current and the configuration fails.


When SelectMAP is used, the BUSY pin does not have to be monitored unless a readback is performed. When downloading an encrypted .bit file to the device, the BUSY pin will toggle. The problem occurs if the BUSY signal from the FPGA is wired to the BUSY pin of the PROM. This occurs because the PROM is pausing the valid data based on BUSY while the FPGA is reading data in. The incorrect data is loaded into the device, which causes internal contention and the device draws excessive current.

If Master Serial is used, the excessive current can be caused in the ES parts by the issues discussed in the Errata. To fix this problem, see (Xilinx Answer 20246).

BIT and NKY files also must be generated with 8.1.01i (I.25) software or later. This release of the software includes an added CRC Check at the beginning of the bit file, and this crc check is not present in earlier releases of the software. If the key loaded in the device does not match the key in the bit file, the download will stop after this first crc check. If older software was used to generate the files and the wrong key or no key is present when the encrypted bit file is loaded, the part can draw excessive current and heat up quickly. The additional code in the .bit file for the encryption process will increase the size of the .bit file approximately 2K bites.

This is not a problem if the incorrect device is targeted. The IDCODE command is still issued in the .bit file to check that the IDCODE of the device matches the IDCODE in the .bit file.

AR# 21777
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article