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AR# 21787

LogiCORE Reed Solomon Decoder v5.1 - How do I increase the clock speeds when implementing the Reed Solomon Decoder?

Description

Keywords: reed solomon, decoder, speed

Urgency: standard

Description:
How do I increase the clock speeds when implementing the Reed Solomon Decoder?

Solution

Hi Chris,

One way of speeding up the core clock speed is to configure it for 2 channel operation and have it process two blocks at a time, with the bytes for each block interlaced. This will allow a higher speed clock but may or may not achieve the required total throughput in this system. Another possibility is just to instantiate 2 cores and have them run in parallel.

Apart from that, it might be possible to squeeze a few MHz with the floorplanner, or playing with map and par options as you suggest. Tying the reset input to gnd and configuring the core without a SR pin may free up some more routing.

I don?t have a pre-built example (for putting 2 RS Decoder cores in parallel). Would it be possible to do it simply with a single de-mux and a toggle flip-flop to control the select every time a sync pulse occurs? Similarly a mux on the output could be switched every time block_start is asserted. This assumes a fixed block length. If N is variable then you will probably need a FIFO on the input.

Bill Wilkie
AR# 21787
Date Created 07/21/2005
Last Updated 05/13/2009
Status Archive
Type General Article