UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 21797

FPGA Configuration - Are there any minimum requirements for CCLK frequency?

Description

General Description:

Are there any minimum requirements for CCLK frequency?

Solution

As long as CCLK frequency and high/low times are met, there are no duty cycle requirements. The CCLK can be run as slow as desired. All of the timing specifications for CCLK are listed in the appropriate device data sheet. The data sheets contain all of the required timing specifications.

AR# 21797
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article