We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 21803

7.1i HDL Parsers - "ERROR:HDLParsers:3281 - "<filename>" Line <line number>. behavioral is not an architecture body for <core_name> in library XilinxCoreLib"


Keywords: IP Update, CORE Generator, COREGen, broken flow, simulation, ISE Simulator

Urgency: Standard

General Description:
When I run the following processes on a file:
- Create a new testbench file
- Check syntax
- Create a new testbench waveform file
- View generated testbench as HDL
- Generate a schematic symbol

the following message occurs in ISE:

"ERROR:HDLParsers:3281 - "<filename>" Line <line number>. behavioral is not an architecture body for <core_name> in library XilinxCoreLib"

This problem only occurs when I am using cores from IP Update 1, 2 or 3. Why does this happen?


The HDL Parser has been updated in ISE 7.1i to make use of the ISE Simulator pre-compiled libraries. Xilinx COREGen simulation does not support the ISE Simulator, resulting in broken flows.

This issue will be fixed in ISE 8.1i Service Pack 1.

In the meantime, there is a patch available for download at:
NOTE: This patch can only be installed AFTER installing Service Pack 4 and IP Update 3.


Extract the archived file, as shown below:

PC :
1. Use any unzip utility to extract the patch files to the %XILINX% installation directory.
2. When asked if you want to replace the files, click "Yes."
AR# 21803
Date Created 09/04/2007
Last Updated 10/16/2008
Status Archive
Type General Article