This Answer Record contains the Release Notes for the LogiCORE Embedded Tri-mode Ethernet MAC Wrapper v3.1, released in 7.1i IP Update #3, which includes the following:
- New Features in v3.1
- Bug Fixes in v3.1
- Known Issues in v3.1
For installation instructions and design tools requirements, see (Xilinx Answer 21938).
New Features in v3.1
- Incorporated more efficient clocking schemes that use fewer BUFGs when possible.
- Added support for both RGMII v1.3 and RGMII v2.0.
- Added optional Clock Enable option that reduces the number of BUFGs in MII mode.
- Added example LOC and PHASE_SHIFT constraints on IDELAYCTRL, IDELAY, and DCM blocks in the HDL for designs that use the RGMII interfaces.
Bug Fixes in v3.1
- CR 209621: Implemented enhanced clocking scheme for MII, GMII and RGMII interface options to fix various problems and reduce BUFG resource requirements.
- CR 209623: Changed the default setting of Tx Enable and Rx Enable options if EMAC is enabled.
- CR 209624: Corrected the CLK_COR_SEQ_1_2 attribute setting in gt11_dual_1000X.v(vhd) for 1000BASE-X and SGMII configurations to be "00001010000".
- CR 209627: Changed RXCLK0_FORCE_PMACLK and TXCLK0_FORCE_PMACLK attributes of the GT11s to "True" in order to not use the low latency mode.
- CR 209640: Added SYNC_ACQ_STATUS to the testbench for 1000BASE-X and SGMII simulations to wait for GT11 PLLs to lock before stimulating the EMAC(s).
- CR 209995: Used TXOUTCLK1 instead of TXPCSHCLKOUT to directly drive RXCRCCLK, RXCRCINTCLK, TXCRCCLK, TXCRCINTCLK when EMAC is configured in 1000BASE-X PCS/PMA and SGMII modes.
- CR 213145: Changed the GT11_MODE attributes from "DONT_CARE" to "A" and from "SINGLE" to "B" to work around PAR failures in 7.1i Service Pack 3 and later when only one EMAC was used.
- CR 213318: Removed the RX_LOS_THRESHOLD attribute from the 1000BASE-X and SGMII versions of the wrappers since this attribute is no longer supported in 7.1i Service Pack 3 and later.
- CR 213578: Implemented enhanced clocking scheme for SGMII and 1000BASE-X PCS/PMA interface configurations to reduce BUFG resource requirements.
- CR 213579: Changed the registers in the Transmit MII logic to be clocked by CLIENTEMAC#TXGMIIMIICLKIN instead of PHYEMAC#MIITXCLK.
Known Issues in v3.1
1. The 16-bit interface option is currently not supported.
2. Designs that use the Virtex-4 EMAC (which have more than 8 BUFGs) fail to be placed in PAR. For more information on this issue and details on how to work around it, refer to (Xilinx Answer 21402).
3. VHDL wrapper contains incorrect clock management for RGMII v2.0 at 10 Mbps, 100 Mbps, and Tri-speed rates. For more information on this issue, see (Xilinx Answer 22019). To resolve this issue, install the patch below and regenerate the wrappers.
4. RGMII configurations are incorrectly reset the IDELAYCTRL module. For more information on this issue, see (Xilinx Answer 22018). To resolve this issue, install the patch below and regenerate the wrappers.
5. Synplify removes the IDELAYCTRL module from RGMII configurations. For more information on this issue, see (Xilinx Answer 22008). To resolve this issue, install the patch below and regenerate the wrappers.
6. The bug fix associated with CR 209995 (see Bug Fixes section above) to use TXOUTCLK instead of TXPCSHOUTCLK for 1000BASE-X PCS/PMA or SGMII configurations did not get fully implemented in the VHDL version. To resolve this issue, install the patch below and regenerate the wrappers.
7. EMAC clock signals might become unrouted in PAR. For more information on this issue, see (Xilinx Answer 22024).
8. A Calibration Block for the Virtex-4 RocketIO must be used with ES devices. Please refer to UG090: Calibration Block User Guide, or contact your FAE for more details and instructions on how to connect the module to the MGTs DRP and other ports. The MGTs in the XAUI core are instantiated in the "gt11_dual_1000X.v/.vhd" file. This file can be modified to instantiate GT11 Calibration Block.
Limitations of demo testbench
- The demo testbench performs only full-duplex simulations, not half-duplex.
- The demo testbench does not simulate the DCR Interface (Host Type = DCR). Only simulations of the Host Interface (Host Type = Host) or no management interface (Host Type = None) are supported.
- If the wrappers are configured in tri-mode (10/100/1000 Mb/s), only 1 Gb/s rates are simulated. The demo testbench does not simulate all three speeds. In order to change the speed, you must use the Host Interface or DCR Interface and change the speed settings in the configuration registers.
- The demo testbench does not support simulations when both EMACs are used with different interfaces. For example, if EMAC0 is configured with the MII interface but EMAC1 is configured with the 1000BASE-X PCS/PMA interface.
- The demo testbench does not support simulation of EMACs when "In-band FCS Enable" option is enabled.
To resolve issues #3, #4, #5, and #6 from the above list of General Issues, apply the following patch to the Xilinx ISE installation with 7.1i Service Pack 4 and IP Update #3:
Install the patch as follows:
1. Extract the contents of the ".zip", ".gtar,gz", or "tar.gz" archive to the root directory of the Xilinx installation. Select the option that allows the extractor to overwrite all of the existing files and maintain the directory structure pre-defined in the archive.
Determine the Xilinx installation directory by entering the following at the command prompt:
UNIX or Linux
Determine the Xilinx installation directory by typing the following:
NOTE: You might need to have system administrator privileges to install the patch.
2. After installing the patch, regenerate the Embedded Tri-mode Ethernet MAC Wrapper v3.1 Core from CORE Generator. The core and supporting files produced will contain the fixes mentioned above.