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AR# 21905

Virtex-4 RocketIO - How do I use the DIGRX_SYNC_MODE attribute?


How do I use the DIGRX_SYNC_MODE attribute?


<> DIGRX_SYNC_MODE enables phase alignment of the PCS XCLK to the PMA XCLK in Digital Oversampled Mode with the Digital CDR. 


<> When the application needs to operate in the low latency mode and has the RXFIFO bypassed, it requires the XCLK domain and the USRCLK domain to be frequency locked. In this case, the USRCLK2 (which come from the fabric) or its /2, /4 derivation will drive the XCLK domain by setting RXCLK0_FORCE_PMA = FALSE. 


Low Latency Clock Path
Low Latency Clock Path


<> The digital oversampling block (DigRx) recovers the clock and delivers it as the 4X,2X,1X digital clocks to the fabric. The 1X clock also becomes the PCS XCLK if the circuit works in *non* low latency mode. The data output from the DigRx block will be synchronized to this PCS XCLK.  


<> In low latency mode, since the PCS XCLK must come from the USRCLK2 (or its /2,/4 derivation). This is essentially the digital clock tree that goes out as RXRECCLK1, then comes back through the fabric. This introduces clock skew compared to the original digital clock. This means the data output from the DigRx will not be phase locked to the PCS XCLK (although they are still frequency locked).  


<> The DigRx block contains a re-timer circuit that re-times the output data to the PCS XCLK that comes from the fabric, the goal here is to incorporate any time delay that the clock could go through in a clock tree used in the fabric, so that the data could be registered correctly in the fabric.  


<> The DIGRX_SYNC_MODE signal enables this retimer circuit in the DigRx block for low latency applications; otherwise, the retimer circuit is bypassed.  


<>If analog CDR is used, the clock phase alignment is handled by the RXSYNC circuit in the PMA, which is not available in the DCDR mode.

AR# 21905
Date 05/19/2014
Status Archive
Type General Article