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AR# 21911

Virtex-4 XtremeDSP Slice and MAP 7.1.03i - Why are the clock enables on my XtremeDSP Slice (DSP48) being disabled? Why is there no output from my XtremeDSP Slice (DSP48), or why is the POUT zero?

Description

Keywords: GND, VCC, AREG, BREG, MREG, PREG, A_REG, B_REG, M_REG, P_REG

Why are the clock enables on my XtremeDSP Slice (DSP48) being disabled? Why is there no output from my XtremeDSP Slice (DSP48), or why is the POUT zero?

Solution

This problem has been fixed in the latest 7.1i Service Pack available at:
http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp
The first service pack containing the fix is 7.1i Service Pack 4.

To work around this issue in ISE 7.1i Service Pack 3, set the following environment variable:
XIL_MAP_NO_DSP_AUTOREG = 1

NOTE: A side effect of this work-around is that registers will not be merged into the XtremeDSP Slice (DSP48), and this might adversely impact performance.
AR# 21911
Date Created 09/04/2007
Last Updated 09/04/2008
Status Archive
Type General Article