This Release Note is for the SPI-4.2 (POS-PHY L4) Lite Core v3.0 released in 7.1i IP Update 3 and contains the following:
- New Features
- Bug Fixes
- Known Issues
For the installation instructions and design tool requirements for 7.1i IP Update 3, see (Xilinx Answer 21938).
New Features in v3.0
Delivered through CORE Generator
Option added to select Source FIFO Burst behavior
Added SnkClksRdy pin to indicate all Sink core clocks are ready for use
Added SrcClksRdy pin to indicate all Source core clocks are ready for use
Added SrcOofOverride pin to assist in board level debugging
Support added for embedded regional clocking
Added signal to indicate when the SysClk DCM loses lock
Added SnkBusErrStat to indicate when non-zero address bits are received on a control word
Bug Fixes in v3.0
CR 186301: The signals SrcFFOverflow_n and SnkFFOverflow_n behave like a Full indication rather than an overflow indication
CR 192231: Updated the range of the Almost Full assert and negate thresholds
(Xilinx Answer 20430) What is the power consumption of SPI-4.2 Lite Core?
(Xilinx Answer 20017) Which I/O Standards are supported for SPI-4.2 Core?
User Guided If you are using multiple SPI-4.2 Cores in a single device, see the "Multiple Core Instantiation" section under the "Special Design Consideration" chapter of the SPI-4.2 Lite User Guide.
Known Issues in v3.0
Core Generation Issues
(Xilinx Answer 21973) Generating the core gives ERROR:coreutil - Parameter c_snk_af_thres_assert value 1 is outside the range 6 to 508.
(Xilinx Answer 21997) GUI swaps "Send Satisfied" and "Send Framing" when generating the core
(Xilinx Answer 22041) ERROR:sim:158 - Tcl error detected while configuring symbol pins, when "ASY Symbol File" option has been selected.
Constraints and Implementation Issues
(Xilinx Answer 22009)) When implementing an SPI-4.2 Lite design through NGDBuild, several "INFO" and "WARNING" messages appear.
(Xilinx Answer 21998) When implementing an SPI-4.2 Lite design through MAP, several "WARNING" messages appear.
(Xilinx Answer 21999) When implementing an SPI-4.2 Lite design through Bitgen, several "WARNING" messages appear.
(Xilinx Answer 22011) There are missing example constraints in the UCF file.
(Xilinx Answer 22000) Example design does not synthesize/simulate with Synplify.
(Xilinx Answer 22012) TSClk unrouted for 3 regional clocks causing unrouted net error in PAR.
(Xilinx Answer 22013) Synplicity synthesis attributes incorrect in User Clk Module causes offset timing error in PAR
(Xilinx Answer 19999) "ERROR:BitGen:169 - This design contains one or more evaluation cores for which bitstream generation is not supported."
General Simulation Issues
(Xilinx Answer 21319) TDat Error: Data mismatch error in timing simulation
(Xilinx Answer 21974) Timing simulation gives RStat Error : DIP2 error received. Expecting 01, recieved 00. SnkDip2ErrReqFlag = 0
(Xilinx Answer 21975) When simulating, the design example testbench will report that DataMaxT was violated.
(Xilinx Answer 22001) Design example gives warnings for source segmenting packets.
(Xilinx Answer 21350) Demo testbench gives RDat Protocal violation warnings.
(Xilinx Answer 21976) For Sink user clocking mode, the Locked_RDClk signal is undefined for the duration of simulation.
(Xilinx Answer 22002) Design example testbench runs at 100 MHz which is too fast for Spartan-3E
(Xilinx Answer 21322) Timing simulation errors: SETUP, HOLD, RECOVERY violations
(Xilinx Answer 22026) Simulating SPI-4.2 Lite design gives, Error: /X_ODDR HOLD Low VIOLATION ON D1 WITH RESPECT TO C;
(Xilinx Answer 20796) When targeting Virtex-4 design with SPI4.2, be advised of silicon issue.
(Xilinx Answer 20022) When fixed static alignment is used, it is necessary to determine the best IOBDELAY (ISERDES) value or the best DCM setting (PHASE SHIFT) to ensure that the target system contains the maximum system margin and performs across voltage, temperature, and process (multiple chips) variations.