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AR# 21922

7.1 System Generator for DSP - Why do I have a cl_clr pin at the top level of my design? My design does not work in hardware after generating a bitstream from the Project Navigator Project when using the HDL Netlist flow. Why?

Description

General Description:

Why do I have a cl_clr pin at the top level of my design? My design does not work in hardware after generating a bitstream from the Project Navigator Project when using the HDL Netlist flow or Bitstream flow. Why?

Solution

When System Generator for DSP 7.1 creates a design, it adds a ce_clr pin that is not necessary for most designs.

To work around this issue, use the HDL Netlist flow. Change the following line in the <design name>_clk_wrapper.vhd:

ce_clr_sysgen <= ce_clr;

to

ce_clr_sysgen <= '0';

This issue is addressed in System Generator for DSP 8.1.

AR# 21922
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article