AR #21946 - LogiCORE Dual Port Block Memory v6.3 - Release Notes and Known Issues for the Dual Port Block Memory Core

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LogiCORE Dual Port Block Memory v6.3 - Release Notes and Known Issues for the Dual Port Block Memory Core

AR#	21946
Topic	Coregen DP Blk Mem
Last Modified	2005-11-04 00:00:00.0
Status	Active

Description

Keywords: CORE Generator, BRAM, ramb16, DP, blkmem, block RAM

Urgency: Standard

General Description:
This Release Note is for the Dual Port Block Memory v6.3 Core released in 7.1i IP Update 3 and contains the following:
- New Features
- Bug Fixes
- Known Issues

For the installation instructions and design tool requirements for 7.1i IP Update 3, see (Xilinx Answer 21938).

Solution

New Features in v6.3
None

Bug Fixes in v6.3
CR 213757 Fixed COE file loading issue

Known Issues
(Xilinx Answer 21982) "ERROR:PhysDesignRules:1088 - Dangling pins on block:<blkmemv2_dp...>" occurs in BitGen.
(Xilinx Answer 22029) Timing simulation gives "ASSERT/ERROR (time 1400 NS) from process :compare_output1".
(Xilinx Answer 22223) Cannot generate the core with falling clock edge.