We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 21946

LogiCORE Dual Port Block Memory v6.3 - Release Notes and Known Issues for the Dual Port Block Memory Core


General Description:

This Release Note is for the Dual Port Block Memory v6.3 Core released in 7.1i IP Update 3 and contains the following:

- New Features

- Bug Fixes

- Known Issues

For the installation instructions and design tool requirements for 7.1i IP Update 3, see (Xilinx Answer 21938).


New Features in v6.3


Bug Fixes in v6.3

CR 213757 Fixed COE file loading issue

Known Issues

(Xilinx Answer 21982) "ERROR:PhysDesignRules:1088 - Dangling pins on block:<blkmemv2_dp...>" occurs in BitGen.

(Xilinx Answer 22029) Timing simulation gives "ASSERT/ERROR (time 1400 NS) from process :compare_output1".

(Xilinx Answer 22223) Cannot generate the core with falling clock edge.

AR# 21946
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article