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AR# 21956

LogiCORE PCI Express- How many initial Posted and Non-Posted credits are advertised by the core? How big is the Memory and I/O Request receive buffer?

Description


General Description: 
How many posted and non-posted header and data credits are initially advertised? What is the size of the Memory and I/O Request buffer?

Solution


The size of the Memory and I/O Request receive buffer is equivalent to the number of initially advertised posted and non-posted header and data credits. 
 
Conversions (PCI Express Spec section 2.6.1): 
1 Header flow control credit = one maximum-size header plus TLP Digest = 20 bytes (64-bit addressable Memory transaction + TLP Digest) 
1 Data flow control credit = 4 DW of data = 16 bytes 
 
There are multiple versions of the PCI Express Core, and each might be different: 
 
v2.0 series PCI Express Core with 64-bit Internal Data Path  
 
Initially advertises: 
120 PH = 120 * 20 = 2400 bytes 
520 PD = 520 * 16 = 8320 bytes 
16 NPH = 16 * 20 = 320 bytes 
16 NPD = 16 * 16 = 256 bytes 
 
The Memory and I/O Request buffer has a maximum of 11,296 bytes or 177 quad-words of space. 
 
v1.0 series PCI Express PIPE Core with 32-bit Internal Data Path 
 
Initially advertises: 
24 PH = 24 * 20 = 480 bytes 
216 PD = 216 * 16 = 3456 bytes 
8 NPH = 8 * 20 = 160 bytes 
8 NPD = 8 * 16 = 128 bytes 
 
The Memory and I/O Request buffer has a maximum of 4224 bytes or 132 double-words or space. 
 
NOTE: In both cores, this buffer is separate from the receiver completion buffer. For more information on the receiver completion buffer, please see Appendix A of the User Guide for each core.
AR# 21956
Date Created 09/04/2007
Last Updated 05/20/2014
Status Archive
Type General Article