Some of the I/O paths driven by a DCM-based clock appears to be missing the DCM component of clock uncertainty. The reported uncertainty is ~25 ps when similar paths have ~205 ps. 205 ~ 50/2(SJ) + 120/2(DCM Jitter) + 120(DCM Phase). When is this going to be fixed?
This problem has been fixed in the latest 7.1i Service Pack available at:
The first service pack containing the fix is 7.1i Service Pack 4.