LogiCORE Dual Port Block Memory v6.3 and Single Port Block Memory v6.2 - "ERROR:PhysDesignRules:1088 - Dangling pins on block:<blkmemv2_dp...>"
Description
Keywords: COREGen, CORE Generator, dual, port, block, memory, BRAM, block RAM, ramb16, dp, blkmem, parameters, BitGen, DRC
Urgency: Standard
General Description:
The Dual Port Block Memory and Single Port Block Memory customization GUI will allow you to select the invalid parameters.
For example: If port A is set as "Write Only", then you should not be able to select optional output register for port A as it will not be applicable.
Another example: If port A is set as "Read Only", then you should not be able to select optional input register for port A or the Write Enable option as they are not applicable.
Selecting these invalid parameters will create cores with unconnected registers. These registers are not flagged in the DRC (Design Rule Check) of ISE 7.1i tool, but will be when running DRC at the beginning of BitGen in ISE8.1i and subsequent versions of the ISE tool. The following DRC error occurs:
"ERROR:PhysDesignRules:1088 - Dangling pins on
block:<blkmemv2_dp_v6_3_sym_combd61341_1_top/BU50/blkmemv2_dp_v6_3_sym_combd6
1341_1_top/BU50>:<RAMB16_RAMB16>. If port B is used the CLKB DIB0 and at
least one address pin ADDRB8-ADDRB13 must be used."
Solution
If you are currently getting the above DRC error, please check the XCO file to see if the core was generated with the incorrect parameter settings. If that is the case, you will need to re-generate the core without the incorrect options.For Dual Port Block Memory core:
On page 1 of the GUI, under Port A Options, if the "Write Only" configuration is selected, then the Output Register Options on page 2 should not be altered (although, the option is available).
On page 1 of the GUI, under Port A Options, if the "Read Only" configuration is selected, then the Register Inputs on page 2 should not be altered (although, the option is available). Write Enable Active High/Active Low on page 2 should not be altered.
On page 1 of the GUI, under Port B Options, if the "Write Only" configuration is selected, then the Output Register Options on page 3 should not be altered (although, the option is available).
On page 1 of the GUI, under Port B Options, if the "Read Only" configuration is selected, then the Register Inputs on page 3 should not be altered (although, the option is available). Write Enable Active High/Active Low on page 3 should not be altered (although, the option is available).
For Single Port Block Memory core:
If "Write Only" or "Read Only" ports are selected, do not alter the parameter settings described above (keep the default settings).