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AR# 21997

LogiCORE SPI-4.2 (POS-PHY L4) Lite v3.0 - GUI incorrectly sets sink almost full mode.

Description

General Description: 

In the GUI, there is an option to choose the Sink Fifo Almost Full mode: 

... Send Satisfied on All Channels 

... Send Framing 

... Send Current Status 

 

When generating the core, this setting is interpreted incorrectly. The behavior of the core in the H/W and the simulation will show incorrect behavior when Sink Fifo as reached the Almost Full condition.

Solution

To work around this issue, adjust the static configuration signal by hand in the wrapper VHDL or Verilog file. 

 

In the wrapper file, search for following comment: 

//**************************************************************************** 

// The following signal instantiations are the User Configuration signals. 

// The user may need to modify these signals to meet their particular 

// application 

//**************************************************************************** 

 

Change the parameter "FifoAFMode" with the following correct value. 

 

The correct value is as follows:  

"Send Framing" should set the parameter to 00 

"Send Satisfied" should set the parameter to 01 

"Send Current Status" should set the parameter to 10 or 11

AR# 21997
Date Created 09/04/2007
Last Updated 05/19/2014
Status Archive
Type General Article