AR #21998 - LogiCORE SPI-4.2 (POS-PHY L4) Lite - When implementing an SPI-4.2 Lite design through MAP, I receive several "WARNING" messages
LogiCORE SPI-4.2 (POS-PHY L4) Lite - When implementing an SPI-4.2 Lite design through MAP, I receive several "WARNING" messages
| AR# | 21998 |
| Part | Coregen POS PHY Lite |
| Last Modified | 2006-07-11 00:00:00.0 |
| Status | Active |
| Keywords | CORE, CORE Generator, COREGen, IP, update, 7.1i, #3, ip3_h,PL4, packet, SONET, physical, link, layer, source, synchronous, phase, alignment, sink, static, spi4.2, spi4-2, lite, quarter, rate, MAP, warnings, info, messages, 8.2i, v4.1 |
Description
Keywords: CORE, CORE Generator, COREGen, IP, update, 7.1i, #3, ip3_h, PL4, packet, SONET, physical, link, layer, source, synchronous, phase, alignment, sink, static, spi4.2, spi4-2, lite, quarter, rate, MAP, warnings, info, messages, 8.2i, v4.1
When implementing a design with an SPI4.2 Lite Core, I receive several MAP warning messages.
The following warnings are harmless and can be ignored.
Solution
Example Warning messages:WARNING:Pack:1185 - One or more I/O components have an illegal combination of
property values. For each occurrence, the system will choose sensible
defaults. To view each occurrence, create a detailed map report (run map
using the -detail option).
WARNING:PhysDesignRules:812 - Dangling pin <CE> on
block:<TStat_P(0)/abcdef_pl4_lite_src_top0/U0/pl4_lite_src_cal0/tstat0_ff>:<D
IFFMI_IFF1>.
WARNING:PhysDesignRules:812 - Dangling pin <SR> on
block:<TStat_P(0)/abcdef_pl4_lite_src_top0/U0/pl4_lite_src_cal0/tstat0_ff>:<D
IFFMI_IFF1>.
WARNING:PhysDesignRules:812 - Dangling pin <REV> on
block:<TStat_P(0)/abcdef_pl4_lite_src_top0/U0/pl4_lite_src_cal0/tstat0_ff>:<D
IFFMI_IFF1>.