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AR# 21998

LogiCORE SPI-4.2 (POS-PHY L4) Lite - When implementing an SPI-4.2 Lite design through MAP, I receive several "WARNING" messages

Description

When implementing a design with an SPI4.2 Lite Core, I receive several MAP warning messages.

The following warnings are harmless and can be ignored.

Solution

Example Warning messages:

WARNING:Pack:1185 - One or more I/O components have an illegal combination of

property values. For each occurrence, the system will choose sensible

defaults. To view each occurrence, create a detailed map report (run map

using the -detail option).

WARNING:PhysDesignRules:812 - Dangling pin <CE> on

block:<TStat_P(0)/abcdef_pl4_lite_src_top0/U0/pl4_lite_src_cal0/tstat0_ff>:<D

IFFMI_IFF1>.

WARNING:PhysDesignRules:812 - Dangling pin <SR> on

block:<TStat_P(0)/abcdef_pl4_lite_src_top0/U0/pl4_lite_src_cal0/tstat0_ff>:<D

IFFMI_IFF1>.

WARNING:PhysDesignRules:812 - Dangling pin <REV> on

block:<TStat_P(0)/abcdef_pl4_lite_src_top0/U0/pl4_lite_src_cal0/tstat0_ff>:<D

IFFMI_IFF1>.

AR# 21998
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article