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AR# 22000

LogiCORE SPI-4.2 (POS-PHY L4) Lite v3.0 - Example design does not synthesize/simulate with Synplify

Description

General Description: 

The SPI-4.2 Lite Core does not synthesize properly with the Synplify synthesis tool. This is due to mistakes in the Synplify project files. Functional and timing simulation also do not work because the Synplify library is incorrectly declared in the wrapper files and example clocking files.

Solution

The following work-around is suggested: 

 

For VHDL:  

- Removal of library declarations in wrapper, and 2 example clocking modules 

- Name substitution required in Synplicity project file "synplify.prj" 

(replace "pl4_" with "pl4_lite_") 

 

For Verilog: 

- Name substitution required in Synplicity project file "synplify.prj" 

(replace "pl4_" with "pl4_lite_")

AR# 22000
Date Created 09/04/2007
Last Updated 05/19/2014
Status Archive
Type General Article