AR #22009 - LogiCORE SPI-4.2 (POS-PHY L4) Lite - When implementing an SPI-4.2 Lite design through NGDBuild, I receive several "INFO" and "WARNING" messages

AR#	22009
Part	Coregen POS PHY Lite
Last Modified	2006-07-11 00:00:00.0
Status	Active
Keywords	CORE, CORE Generator, COREGen, IP, update, 7.1i, #3, ip3_h,PL4, packet, SONET, physical, link, layer, source, synchronous, phase, alignment, sink, static, spi4.2, spi4-2, lite, quarter, rate, NGDBuild, info, warning, message, v4.1, 8.2i

Solution 1

Warnings that cannot be ignored:

WARNING:NgdBuild:488 - Attribute value "default" is not an accepted value for
attribute "IOSTANDARD" on "LoopbackClk_ibufg0".
WARNING:NgdBuild:488 - Attribute value "default" is not an accepted value for
attribute "IOSTANDARD" on "pl4_lite_src_clk0/sysclk_ibufg0".
WARNING:NgdBuild:488 - Attribute value "default" is not an accepted value for
attribute "IOSTANDARD" on "TStat_ibuf0".
WARNING:NgdBuild:488 - Attribute value "default" is not an accepted value for
attribute "IOSTANDARD" on "TStat_ibuf1".
WARNING:NgdBuild:488 - Attribute value "default" is not an accepted value for
attribute "IOSTANDARD" on "RStat_obuf0".
WARNING:NgdBuild:488 - Attribute value "default" is not an accepted value for
attribute "IOSTANDARD" on "RStat_obuf1".
WARNING:NgdBuild:488 - Attribute value "default" is not an accepted value for
attribute "IOSTANDARD" on "RSClk_obuf0".
WARNING:NgdBuild:488 - Attribute value "default" is not an accepted value for
attribute "IOSTANDARD" on "CalClk_ibufg0".
WARNING:NgdBuild:488 - Attribute value "default" is not an accepted value for
attribute "IOSTANDARD" on "pl4_lite_src_clk0/tsclk_ibufg0".

In the SPI-4.2 Core, the I/O Standards are not defined in either the netlists or in the UCF; therefore, all differential signals default to LVDS 2.5 Volt without the internal device termination. All single-ended signals will default to LVCMOS. Therefore, the above "IOSTANDARD" attribute warnings must be addressed by specifying the proper I/O standard of the reported input and output buffers. To define the I/O standard for these buffers, add new constraints to the UCF file.

For example, to define the I/O standard for the RSClk output buffer, add the following constraint to the UCF:

INST "RSClk_ibuf0" IOSTANDARD = LVTTL;

In Virtex-4, the ISE tool defaults all single-ended non-declared I/O to LVCMOS25, which is not supported for the SPI-4.2 Core. Please refer to (Xilinx Answer 20017) for a list of I/O standards supported by the SPI-4.2 Core and information on defining the I/O standards in the UCF.

In the next SPI-4.2 Core release, the I/O standards will be pre-defined.

Solution 2

INFO messages that can be ignored:
INFO:XdmHelpers:851 - TNM "RDClk_P", used in period specification "TS_RDClk_P",
was traced into DCM_ADV instance "pl4_lite_implv4_allcomb79820_14_pl4_lite_snk_top0/U0/pl4_lite_snk_clk0/rdclk_dcm0". The following new TNM groups and period specifications were generated at the DCM_ADV output(s):
CLK0:
TS_pl4_lite_implv4_allcomb79820_14_pl4_lite_snk_top0_U0_pl4_lite_snk_clk0_RDClk0_dcmo=PERIOD
pl4_lite_implv4_allcomb79820_14_pl4_lite_snk_top0_U0_pl4_lite_snk_clk0_RDClk0_dcmo TS_RDClk_P*1.000000 PHASE + 1.425000 nS HIGH 50.000000% INPUT_JITTER 300.000000 pS

INFO:XdmHelpers:851 - TNM "SysClk_P", used in period specification "TS_SysClk_P", was traced into DCM_ADV instance "pl4_lite_src_clk0/tdclk_dcm0". The following new TNM groups and period specifications were generated at the DCM_ADV output(s):
CLK0:
TS_pl4_lite_src_clk0_SrcClk_dcmo=PERIOD
pl4_lite_src_clk0_SrcClk_dcmo TS_SysClk_P*1.000000 HIGH 50.000000% INPUT_JITTER 200.000000 pS
INFO:NgdBuild:738 - A case sensitive search for the INST, PAD, or NET element referred to by a constraint entry in 'pl4_lite_implv2p_64b_sburst65707_3_top.ucf' that accompanies this design has failed, while a case insensitive search is in progress. The result of the case insensitive search will be used, but messages will accompany each and every use of a case insensitive result. Constraints are case sensitive with respect to user-specified identifiers, which includes names of logic elements in a design.
INFO:NgdBuild:739 - Line 110 in 'pl4_lite_implv2p_64b_sburst65707_3_top.ucf':
Found case insensitive match for INST name 'pl4_lite_implv2p_64b_sburst65707_3_pl4_lite_snk_top0/U0/pl4_lite_snk_io0/rdat_clk180*'. INST is
'pl4_lite_implv2p_64b_sburst65707_3_pl4_lite_snk_top0/U0/pl4_lite_snk_io0/RDat_Clk180_*'.

INFO:NgdBuild:739 - Line 109 in 'pl4_lite_implv2p_64b_sburst65707_3_top.ucf':
Found case insensitive match for INST name
'pl4_lite_implv2p_64b_sburst65707_3_pl4_lite_snk_top0/U0/pl4_lite_snk_io0/rdat_clk0*'. INST is
'pl4_lite_implv2p_64b_sburst65707_3_pl4_lite_snk_top0/U0/pl4_lite_snk_io0/RDat_Clk0_*'.

Solution 3

Warnings that can be ignored:

WARNING:NgdBuild:440 - FF primitive 'test_pl4_lite_src_top0/U0/pl4_lite_src_synchronizer0/src_src_statclk_en_sync/output_ff' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive 'test_pl4_lite_src_top0/U0/pl4_lite_src_synchronizer0/src_srcclk_en_sync/output_ff' has unconnected output pin