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AR# 22023

LogiCORE (POS-PHY Level 4) SPI-4.2 v7.3 - Timing simulation fails in start-up sequence for SPI-4.2


General Description: 

When simulating a design example, I receive the following errors at 100 ns: 


 # ** Error: Timing Violation Error : RST on instance * must be asserted for 3 CLKIN clock cycles.  

 # Time: 100 ns Iteration: 1 Instance: /pl4_demo_testbench/pl4_wrapper0/pl4_implv4_64b_11dyn68458_2_pl4_src_top0_u0_clk0_tsd


You will see this error when you select core performance of 1 Gbps and the internal clock generator option PMCD for the sink or source core. 


The maximum performance of PMCD is 450MHz (not 500 MHz). Therefore, if the performance of 1 Gbps is needed, you must select DCM for your internal clock generator.

AR# 22023
Date Created 09/04/2007
Last Updated 05/19/2014
Status Archive
Type General Article