LogiCORE Dual Port Block Memory v6.3 - Mismatch on both DOUTA and DOUTB for the DPBLKMEM for V-4 using NCSIM
Description
Keywords: CORE, COREGen, CORE Generator, dual, port, block memory, block RAM, BRAM, ramb16, dp, blkmem, dout, douta, doutb, ncsim, simulation, timing issue
Urgency: Standard
General Description:
When simulating Dual Port Block Memory v6.3, targeting the Virtex-4 family and using NCSIM LDV 5.1 simulator, I receive the following ERROR message:
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ncsim> run
ASSERT/ERROR (time 1400 NS) from process :compare_output1 (architecture work.testbench:xilinx)
VHDL ( 01 ) /= Netlist ( 11 ) on DOUTA
Assertion at 1400 NS + 1
./svg_tb_blkmemdp_v6_3.vhd:1583 ASSERT doutavhdl = doutanetlist
ncsim> exit
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Solution
This issue occurs when you target the Virtex-4 family, with the SDF file, and use NCSIM.It does not occur with the Virtex-II family or when you run the simulation without the SDF file.
This issue is still under investigation. If you encounter this issue and need assistance, please, contact Xilinx technical support.