UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 22042

LogiCORE SPI-3 PHY v4.0 - DCM placement constraints needed in UCF (alos applies to SPI-3 Link core)

Description

Urgency: Standard  

 

General Description: 

When running PAR with the SPI-3 PHY Core, the clock pin and DCM will be placed on opposite sides of the chip, causing timing failures due to large clock delays.

Solution

To resolve this issue, you will need to lock down the DCM near the SPI-3 Core. Add the placement constraint for the DCM and the clock pin.

AR# 22042
Date Created 09/04/2007
Last Updated 05/19/2014
Status Archive
Type General Article