8.2i XST - Using the same integer variable for two separate loops generates an incorrect netlist
Description
Keywords: combinatorial, process, Verilog, 8.1i, 7.1i
Using two "for" loops with the same integer variable, even if they are in two separate processes, generates an incorrect netlist.
The following example generates an incorrect netlist:
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module test_broken(a, y);
// Inputs and outputs
input [7:0] a;
output [7:0] y;
// Declare variables
reg [7:0] r;
reg [7:0] y;
// Declare iterator
integer i;
// Reverse input
always @(a) for (i = 0; i < 8; i = i + 1) r[i] = a[7-i];
// OR with mask 10101010
always @(r) for (i = 0; i < 8; i = i + 1) y[i] = r[i] | i[0];
endmodule
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Solution
To work around this issue, use two separate integer variables as follows:========================================================
module test_working(a, y);
// Inputs and outputs
input [7:0] a;
output [7:0] y;
// Declare variables
reg [7:0] r;
reg [7:0] y;
// Declare iterators
integer i, j;
// Reverse input
always @(a) for (i = 0; i < 8; i = i + 1) r[i] = a[7-i];
// OR with mask 10101010
always @(r) for (j = 0; j < 8; j = j + 1) y[j] = r[j] | j[0];
endmodule
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This issue is scheduled to be fixed in ISE 11.1.