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AR# 22070

IP_Processors - PAR Error occurs when implementing an EDK System using the OPB DDR V2.00.b


Urgency: Hot 


General Description: 

When I use the OPB DDR v2.00.b in EDK 7.1 with Service Pack 2, for an Embedded System targeting the Virtex-4 FX or Virtex-II Pro, the following PAR Error occurs: 


" * TSCLK2CLK90_DDR_SDRAM_64Mx32 = MAXDELAY FROM TIMEGRP "OPB_Clk_DDR_SDRAM_64Mx32" TO TIMEGRP "Device_Clk90_in_DDR_SDRAM_64Mx32" 2.5 ns " 


The OPB Frequency is 100 MHz in this particular case.


This Timing Constraint is no longer needed. The problem will be fixed in EDK 8.1. 


To work around this problem, do the following: 


1. Browse to the following folder: 


(Where C:\EDK is your EDK 7.1 SP2 install directory.) 


2. Open "ddr_v2_1_0.tcl" using any text editor. 


3. Search for the following line: 

puts $outputFile "TIMESPEC \"TSCLK2CLK90_$instname\" = FROM \"${clk_name}_$instname\" TO \"Device_Clk90_in_$instname\" $clk_period_ns ns;" 


4. Type a # in front of this line to comment it out. The Line should look similar to the following: 

 # puts $outputFile "TIMESPEC \"TSCLK2CLK90_$instname\" = FROM \"${clk_name}_$instname\" TO \"Device_Clk90_in_$instname\" $clk_period_ns ns;" 


5. Save and Close the file. 


6. Re-run PlatGen in XPS; the PAR Timing Error should disappear.

AR# 22070
Date Created 09/04/2007
Last Updated 05/19/2014
Status Archive
Type General Article