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AR# 22071

7.1i Schematic - Schematic symbols (IDDR, ODDR, ISERDES, OSERDES) contain incorrect INIT parameters which cause simulation errors

Description

The HDL Functional Model created from schematics contains invalid INIT attributes for IDDR, ODDR, ISERDES, and OSERDES. The generated code makes the init values a string, but they should be integer or bit.

Solution


To work around this issue, you can manually edit the ".vf" or ".vhf" files to change the init values from string to bit.



For VHDL, the ".vhf" file contains:



generic( INIT_Q1 : string := "0";

INIT_Q2 : string := "0";

DDR_CLK_EDGE : string := "OPPOSITE_EDGE";

SRTYPE : string := "SYNC");





This can be changed to:



generic( INIT_Q1 : bit := '0';

INIT_Q2 : bit := '0';

DDR_CLK_EDGE : string := "OPPOSITE_EDGE";

SRTYPE : string := "SYNC");





For Verilog, the ".vf" file contains:



defparam DDR_ADCLK.INIT = "0";



The correct syntax is:



defparam DDR_ADCLK.INIT = 0;





This issue has been corrected in ISE 8.1i.
AR# 22071
Date Created 09/04/2007
Last Updated 01/27/2011
Status Archive
Type General Article