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AR# 22084

LogiCORE SPI-4.2 (POS-PHY L4) v7.3 - Sink core goes Empty when there is 1 packet left in FIFO


Urgency: Hot  


General Description: 

When using SPI-4.2 Sink core targeting Virtex-4 (v7.0, v7.1, v7.2, v7.3), the Sink core indicates that the sink FIFO is empty when there is a burst of data left in the FIFO. There are different data patterns which will cause the issue, but the problem manifests itself only when the Sink core receives one of these data patterns and immediately stops receiving additional data. If the Sink core receives another burst, both the "stuck" burst and the new burst will come out of the core. 


This issue must be addressed by installing the patch.


This problem is fixed in the SPI4.2 v7.3 patch. 


For more information, see (Xilinx Answer 22238).

AR# 22084
Date Created 09/04/2007
Last Updated 05/19/2014
Status Archive
Type General Article