We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 2209

V1.4.0 CORE Generator: Foundation Schematic Flow


Keywords: DSP, COREGEN, Core Generator, Foundation, coregen, cogenend

Urgency: Standard

How to generate CORE Generator modules when using a Foundation
Schematic Flow.



1) Create a New Project or Select an existing Project from
the Foundation Project Manager. The files generated by CoreGen
will automatically be copied into the selected project directory.

2) Start Coregen from the Start Menu, and from the menu Options->Output
Format, select the following options:


- Foundation Symbol
- XNF Netlist

3) Check that all your paths are set properly under Options->System Options.
If one or more of the paths are not set properly, you can modify it/them in this

4) Select the module that you want to generate by double clicking on the icon.

5) For each module, a Data Sheet is available. Click on the green and yellow
icon labeled "Spec" to access the Data Sheet. The module Functional Description
is included in the data sheet.

6) Fill out the fields as described in the CORE Generator
parameters section of the data sheet and click on GENERATE.

7) A Foundation symbol and a Xilinx Netlist File (.XNF) will
be created.

- The symbol is automatically copied to the Active Project
directory and can be added to the top level schematic from the
Symbol menu after selecting File->Update Libraries from
the Foundation Schematic Editor window.

- The XNF file is also copied to the Active Project directory
as well as the Coregen working directory.

8) The Module Symbol can be added to the Top Level schematic
like any other symbol. The simulation and compilation flow
are the same as the standard Unified Library flow (M1 or

Please refer to the Foundation Online Documentation for
further information.


*** CONCEPT-only users (not using Synergy):

download patches #1, 2, 3, 4 and 5:

(picXilFlow, xilNetlist, PICTools, xilVerilogLib,
and xilConceptLib.



Download patches #3, #4, and #6

(PICTools, xilVerilogLib, and xilComposeLib).

NOTE: Composer libs do not include 4000E or 5200 support.


*** Verilog-only users:

a. If you are using the ES-Verilog interface,

1) you should be using the netlisters funcnetx, timenetx,
xnf2verilog, and xcdsprep from the Xilinx 5.2.1 CD--this
contains the latest version of these programs.

2) download #4, extract, and copy
./share/library/xilinx/verilog* to $XILINX/data.

b. If you are using the Cadence Verilog interface shipped by
Cadence and you are doing Verilog entry and simulation
only, download #1, #2, #3, and #4.
AR# 2209
Date Created 05/27/1997
Last Updated 08/16/1999
Status Archive
Type General Article